High Performance Reconfigurable Computing

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Seeking Speed: Hardware versus Software       

Computer applications mobilize hardware and software resources in order to perform processing as efficiently as possible. Processing consists of sequences of instructions. Those that are engraved in the silicon of processors (CPU, central processing unit) deliver optimum performance, whereas software provides the flexibility required for specific functional programming, but with much lower performances. The ASIC (application-specific integrated circuit) technology allows specific applications to be hard-wired, thus offering the speed of silicon, but development costs and time to market mean this solution is only truly feasible for mass-produced applications whose specifications can be frozen, in exchange for a low cost price per unit. ASIC integrated circuits – much like GPUs (graphics processing units) – outperform software, but cannot offer the flexibility provided by the latter.

Reconfigurable Computing

FPGA (field-programmable gate array) circuits have shattered this dilemma by making it possible to reconfigure electronic circuits via programming, giving rise to the field of reconfigurable computing. These circuits mainly contain elementary logic functions (AND, NAND, OR, XOR, XNOR, etc.) that are interconnected by programming (HDL: hardware description language) in order to provide algorithms that are comparable to a computer program. The FPGA technology therefore allows direct programming of an electronic circuit, providing the performance of specialized integrated circuits while offering the flexibility that was once specific to software. However, the spectacular rise in the execution speeds of these circuits is mainly due to their capacity to perform massively parallel processing, so that a single FPGA can now rival several hundred CPUs.

FPGA: High Performance Computing for Finance

For the same electric consumption, FPGAs easily outperform CPUs and GPUs, in particular in applications that can be massively parallel such as those used in the fields of finance and insurance. Advances in the modeling of complex financial instruments, combined with the risk control constraints imposed by governments and regulatory agencies, have led to a major demand for computing power, and as a consequence, steadily rising energy costs. The classical approach, which consists in clustering standard, low-cost computers in computing grids, quickly runs into practical limitations in terms of electrical consumption, storage space, cooling capacity and maintenance costs. But more importantly, there is a theoretical limit to extending the grids: it lies in the speed at which the processors can communicate. Beyond a certain size, adding new computers only marginally improves global performance. Porting the part of the algorithms that can be parallelized onto FPGA – precisely the part that requires intensive computing – meets the challenges of HPC by overcoming the limitations of computing grids while drastically reducing the carbon footprint.

 

Performance of Monte-Carlo Simulation (C. Delivorias)

References

Delivorias, C.: Case studies in acceleration of Heston’s stochastic volatility financial engineering model: GPU, cloud and FPGA implementations. Master’s thesis, The University of Edinburgh (2012).

de Schryver, C., Shcherbakov, I., Kienle, F., Wehn, N., Marxen, H., Kostiuk, A., Korn, R.: An energy efficient FPGA accelerator for Monte-Carlo option pricing with Heston model. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, pp.468-474 (2011). doi: 10.1109/ReConFig.2011.11.

Sridharan, R., Cooke, G., Hill, K., Lam, H., George, A.: FPGA-based reconfigurable computing for pricing multi-asset barrier options. In: Proceedings of Symposium on Application Accelerator in High-Performance Computing PDF (SAAHPC), Chicago, IL (2012).

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